Typically, dynamic random access memories (DRAMS) are comprised of two components, array and periphery. The array is repetitively densely patterned on a semiconductor chip and each array includes a memory cell and associated decoders. The periphery, which contains most of the remaining circuitry required for operation is placed only once on the chip.
FIG. 1 illustrates a simplified top view of a conventional DRAM layout. As shown, array 2 is patterned many times on semiconductor chip 6 around periphery circuitry 4 which is patterned only once and in a centered position on chip 6. In the past, in order to achieve the layout illustrated in FIG. 1, masks were used which were made by stepping a single chip pattern onto a mask many times via optical lithography. The masks were then used in a one-to-one projection printer in realizing the desired design in on a semiconductor chip. Thus, each exposure of a mask onto a semiconductor slice generated the patterns for many chips from the slice simultaneously. With today's direct-step-on-wafer machines, one chip or a group of chips is exposed at a time. A pattern can be stepped on either a reticle or upon a wafer using a reticle via a method of e-beam lithography.
The proper fabrication of semiconductor mask reticles in the era of 16 megabit dynamic random access memories (DRAMS) and beyond presents many problems Today, reticles are fabricated using e-beam lithography techniques. These techniques require every geometry to be individually written directly into the reticle. At the 16 megabit level of integration, each reticle takes between 1 hour and 2 hours of time to write. In addition, due to the high accuracy requirements imposed by such high levels of semiconductor integration and due to the mean time between machine failure, a number of passes are required. Sometimes as many as 5 passes are required to get one non-defective reticle. This is true of the most advanced e-beam machine More conventional e-beam machines require on average, even a greater number of passes.
Documented cases have shown that at the 16 megabit level, over 3 months of mask making time is required to get a complete reticle set. This is a long time considering the fact that the reticle formation was a high priority task unto which many resources were available.
As DRAM densities continue to increase, the problems of reticle formation continue to get worse. When the magnitude of data increases and the size of the geometries get smaller, the resulting complexity increases by about one order of magnitude per generation of DRAM. Consequently, using conventional techniques, although reticle formation is difficult at the 16 megabit level, it will be almost impossible at the 64 megabit level, and certainly out of the question at the 256 megabit level.